Not applicable.
1. Field of the Invention
The present invention relates to the reducing of timing uncertainties in high-performance multiple channel devices. More specifically, the present invention relates to a device and method for minimizing timing uncertainties due to asymmetry of rising and falling edges and also duty cycle inaccuracy. The invention can be employed in a digital interface between two items or within a circuit where there is a requirement for tight timing control such as requirement for a low skew between the channels of a register.
The present invention is particularly applicable to digital systems of data transmission, interfaces to memory devices, to test equipment for testing semiconductor devices and to high-speed communications, especially for systems with double data transmission rate (DDR).
2. Description of the Related Art Including Information Disclosed Under 37 CFR 1.97 and 1.98
Transistor linewidths have been reducing according to Moore""s Law since around 1971: this involves a doubling of the density of transistors every 18 months. The speed of a transistor, such as a MOSFET, is proportional to the inverse of the square of the channel length, which means that many integrated circuits are now able to operate at speeds above 1 GHz internally. Except for a small number of extremely complicated interfaces, or for serial interfaces, the interface speeds have been a small fraction of the maximum chip operating speed. Another problem has been the width of the interface: the problem of skew between signal lines has hitherto prevented wide interfaces from operating at high frequency, hence creating a fundamental limit to the bandwidth than an interface can carry.
In another example, that of Automatic Test Equipment (ATE), a substantial complexity of deskew circuitry has been required to test high speed devices. Moreover, as soon as the device is under test, the heat generated by the environment of the drivers, the drivers themselves and other factors has caused the skew to alter during the test.
Known is the use of analogue increments to automatically self-calibrate a pulse generator described in U.S. Pat. No. 5,430,660. During the calibration, the output of the oscillator is used to produce output pulses whose edge locations are then adjusted by small digital increments or xe2x80x9csliversxe2x80x9d and very small analogue increments or xe2x80x9cverniersxe2x80x9d. The RAM contents are converted to a serial bit stream that controls the coarse pulse width and period as an integral number of top octave periods, or quanta. However, this method of skew control is not automatic and requires an operator to disconnect the generator from the working circuit and connect an output of the generator to a calibration input in order to accomplish the calibration.
It has been a growing tendency in high speed communications, in particular, digital systems of data transmission, to increase data transmission rates and timing accuracy. However, as frequency grows, a problem arises of accurate and reliable reading of previous and subsequent symbols by various devices for receiving and transmitting data.
For digital circuit devices such as flip-flops, latches and other storage circuits, accurate reading of signals is possible only provided strict requirements to set-up and hold times are observed, where xe2x80x9cset-up timexe2x80x9d is the time before the clock edge during which data are required to be present and stable, and xe2x80x9chold timexe2x80x9d is the time after the clock edge during which data are required to be present and stable. These requirements result in that the maximum clock frequency is limited by the sum of hold and set-up times; therefore, it is desirable that set-up and hold time be as short as possible.
Different attempts have been made to improve setup and hold time characteristics, however, a thorough analysis of component elements of setup/hold times is absent in the available art, therefore, it would be helpful to gain a better understanding of phenomena taking place at that.
In FIG. 7a, a block scheme of a real flip-flop is presented, which consists of an ideal flip-flop FF which is noiseless, hysteresis-free and has zero setup and hold times. A real flip-flop additionally comprises delays Td and Tc in data and clock paths, respectively. Also, there is a source N of phase noise in clock path and a source of hysteresis H.
The delays Td and Tc depend on such parameters as temperature, supply voltage, direction of transition (rising or falling edge), frequency of signal and others. The combination of Td and Tc gives a value of setup/hold time which provides stable data transmission. For example, assuming Td varies from 0 to 1 ns, Tc varies from 0 to 1 ns, each independently, it would be impossible to read data earlier than 1 ns after the change occurs, with respect to clock, or less than 1 ns before the change that gives the values of setup time=1 ns, hold time=1 ns. Furthermore, phase noise extends setup and hold times for the value of phase noise.
Flip-flops are often used to synchronize signals operating at different frequencies to a local clock. However, since the signals are asynchronous to the local clock, the setup and hold time specifications associated with the flip-flop are sure to be violated. When the setup and hold time is violated, the output response of the flip-flop is uncertain. The output may assume a xe2x80x9cmetastablexe2x80x9d state, defined as the time period during which the output of a digital logic device is not at logic level 1 or logic level 0, but instead resides at an output level between logic level 0 and logic level 1. The voltage ranges corresponding to different logic levels are specified by the manufacturer of the device. For bipolar TTL technology, for example, the metastable region might lie between 0.8 volts and 2.0 volts.
The metastable problem occurs when the signal being input to the flip-flop is undergoing a transition from one logic level to the other simultaneously with the active edge of the local clock pulse, causing the latch section of the flip-flop to latch at the intermediate voltage level. Since the input data is changing while it is being clocked, the system designer does not care if the flip-flop goes to either a high or low logic level in this instance, just so long as the output does not xe2x80x9chang-upxe2x80x9d in the metastable region. Eventually, the output of the flip-flop will stabilize at a valid logic level; however, logic circuitry following the flip-flop depends upon the delay specification (stated time period from the clock pulse to a valid output) being met. A metastable output may cause this logic circuitry to fail. Thus, the metastable characteristics of the flip-flop used to synchronize an asynchronous data stream can influence overall system reliability.
One approach to mitigate the problem of metastable outputs is to provide a second flip-flop in series with the first flip-flop, or more flip-flops cascaded as proposed in U.S. Pat. No. 4,929,850. The clock to the second flip-flop is delayed relative to clock to the first flip-flop, thus allowing time for the output signal of the first flip-flop to stabilize at a valid logic level before clocking the data into the second flip-flop. In many applications, this delay is excessive. Furthermore, the logic may still fail if the output of the first flip-flop remains in the metastable region for a period greater than the delay between the clocks.
Thus, the traditional solution of employing two serially connected flip flops is not desirable in applications where an output is needed rapidly. The use of the second flip flop delays the resulting output by an entire clock period. In order to rapidly provide this output, it has also been proposed to rapidly resolve internal logic signals through the use of the deselect synchronizer, instead of two flip flops.
Another approach is described in U.S. Pat. No. 6,002,282 according to which a closed-loop clock delay adjustment system compensates the difference between the delay introduced by on-chip clock buffers and delays inserted at the device data input pins. By measuring the actual real time drift, the clock buffer delay is adjusted to minimise the input set-up time without additional requirements to hold time. The value of Tc is adjusted at a rising edge with the same value of Td that provides a significant reduction in setup/hold time.
However, even after the adjustment is made, there are still phase noise and asymmetry of the rising and falling edges that influence the setup/hold time.
Moreover, the moment of reading data depends also on frequency because the system described in U.S. Pat. No. 6,002,282 uses as a reference an internal clock of high frequency which is inaccurate to the extent it is frequency dependent, because a high frequency clock has additional frequency-dependent phase errors due to system parasitics.
One more source of errors is the hysteresis at the receiver which increases setup/hold time for the value of hysteresis. However, still the most important phenomena that has not been taken into consideration until now, but yet influencing the accuracy of operation of a digital device is that each flip-flop, latch and similar device can be defined by its inherent probability function of transition from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d depending on set-up and hold times.
In FIG. 10a is shown a sequence of symbols S1-Sn transmitted through a channel, where the former symbol S1 changes to the next symbol S2 at a moment xe2x80x9cOxe2x80x9d.
Let us consider in more detail the moment of transition from signal S1 to signal S2 with reference to FIG. 7c. 
The probability of reading symbol S2 when the time is much less than xe2x80x9c0xe2x80x9d is equal to 0%, the same as the probability of reading symbol S2 at times much more than xe2x80x9c0xe2x80x9d is equal to 100%, while in time interval near 0, the probability changes smoothly from 0% to 100%, with value of 50% at time 0. This phenomenon is caused by system noise and other static errors and because of this, has a probabilistic nature.
It can be approximated by the following function:       P    ⁢          (      t      )        =            1      +              Erf        ⁡                  (                      t            /            σ                    )                      2  
where txe2x80x94is the moment of reading data;
Pxe2x80x94is the probability function;
"sgr"xe2x80x94is rms (root-mean-square) value of phase noise.
An example probability function for a typical flip-flop is shown in FIG. 7b, where P is the probability, and t is the time difference between the actual moment when the data is read and the moment when the data crosses a threshold of the flip-flop. It is possible to measure this probability function experimentally, e.g. using procedure described in details in WO 00/00837, published on Jun. 1, 2000, the description of which is incorporated herein by reference.
For different moments of reading data, the probability of reading either new or previous data changes gradually from 0 to 100% of the time defined by the value of phase noise of the system in whole, so that a selected range of xcex94P would correspond to a predetermined level of timing uncertainty. It shall be mentioned that the term xe2x80x9ctiming uncertaintyxe2x80x9d relates to uncertainty of the moment of reading data caused by different reasons including phase noise, static input offset and others and reflects the total effect caused by a sum of these factors.
Thus, another term of high importance which is used within the context of the present invention and closely related to the uncertainty in reading data is xe2x80x9ca probability of reading a desired symbol on a boundary of two symbols in a sequence of symbols transmitted through a channelxe2x80x9d. It is obvious from the figure, that if the placement of the moment when the data is read on the probability function of transition from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d is not controlled, no reliable data is obtained.
The above-described problems are exacerbated as timing tolerances become more severe with higher data transfer rates. For example, if the data clock does not latch the data applied at the proper time, data errors may result. Similar problems exist in many memory devices, such as synchronous DRAMs, and contemporary microprocessors which must process control and other signals at a high rate of speed.
Unfortunately, there has heretofore been no suitable means for ensuring that digital signals are latched in high speed digital interfaces in proper time at very high data transfer rates.
In PCT/RU00/00188 filed in the name of the applicant of the present invention, a timing control means is described for the compensation of timing errors in multiple channel devices wherein for each register a corresponding feedback loop is associated for the relative alignment of register""s channels timing in relation to the reference signal, said feedback loop comprising a means for detecting a deviation from a predetermined level of probability of reading by the register a desired symbol on a boundary of two reference channel symbols in a sequence to generate a feedback signal to compensate timing errors in said register.
By measuring real values of the probability function of transition from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d, according to PCT/RU00/00188, the actual moment of reading data may be determined with the accuracy equal to a very small fraction of the value of the phase noise causing this uncertainty that makes possible highly accurate (up to subpicoseconds) placement of the average position of the moment of reading data.
However, the obtained accuracy is often insufficient when waveforms are asymmetrical with respect to the rising and falling edges. Another common problem for high speed data transmission is the inequity of duty cycles that is especially sensible in DDR systems.
The object of the invention is the provision of a high speed digital interface having multiple channels, in which digital signals are latched at the proper time at very high data transfer rates and that would be insensible to the asymmetry of waveforms and inequity of duty cycles and other signal errors, as well as a system phase noise.
Thereby, an interface is provided involving drivers and receivers to have the minimum or predefined skew, regardless of whether that interface is within the same chip, within the same circuit board, or in different locations in the globe.
The advantages of the present invention is a great reduction in the cost and complexity of high speed interfaces, combined with an increase in the potential bandwidth. For example, the RAMBUS interface is essentially a serial interface straining the technology available to provide 9 to 18 bits of high speed parallel transfer. The present invention would involve no strain of technology, and give a bandwidth which could be one or two orders of magnitude higher than the fastest RAMBUS components available today. At another level, an ATE system could reduce by an order of magnitude the cost of the skew control circuitry, which forms a very large part of the cost of a test head.
The invention concerns the control of timing within a register. The register may have any number of outputs. For example, the invention enables any number of registers to have the same skew, which can even be controlled to be zero at all times during its operation.
In one aspect, the invention is a timing control means for the compensation of timing errors in multiple channel devices comprising at least one register, the means comprising a clock for providing a clock signal; a reference signal generator for providing a reference signal applicable through a reference channel to the register for deskewing the register""s channels; wherein for each said register a corresponding feedback loop is associated for the relative alignment of register""s channels timing in relation to the reference signal, said feedback loop comprising a means for detecting a deviation from a predetermined level of probability of reading by the register a desired symbol on a boundary of two reference channel symbols in a sequence and a set of delay means which uses the determined information on deviation from the fixed level of this probability to generate a feedback signal to compensate timing errors in said register.
The invention uses a channel of the register to take a reference signal which is offset in phase from the register""s clock. For example it can be the clock signal delayed by a stable structure such as a pcb track. The output of the register taking this reference channel is applied to an integrator which implements the detecting means to create a negative feedback signal which is applied to a delay circuit with a monotonic transfer function on the clock input to the register.
In the diagram of FIG. 10c, which is called an eye diagram, an interval of timing uncertainty is shown with respect to the probability function of FIG. 7b. Increases in phase offset between the sampling point and the transition of the reference signal will create a pulse stream and the system will adapt to operate on a predetermined level of probability, which may be chosen as, e.g. the point where there is the maximum uncertainty, which means that 50% of the values are 0 and 50% are 1 in a binary digital system. This point is close to or the same as the point where metastability occurs and may include metastable phenomena in susceptible registers. For a description of metastability, refer to xe2x80x9cMetastability and the ECLinPS(trademark) Familyxe2x80x9d by Rennie Wm. Dover and Todd Pearson, AN1504, Motorola Inc., 1996; and also xe2x80x9cHigh-Speed Digital Design: A Handbook of Black Magicxe2x80x9d by Howard W. Johnson and Martin Graham, Prentice Hall PTR, 1993, Englewood Cliffs, N.J. 17632.
In another aspect of the invention, a self calibrating receiver comprises a register having a plurality of channels having inputs and outputs; a clock for providing a clock signal to the register; a reference signal generator connectable to the input of at least one said channel of said register for supplying reference signals for deskewing the register; a detecting means connectable to the output of at least one said channel of said register for detecting a deviation from a predetermined level of probability of reading by said register a desired symbol on a boundary of two reference channel symbols in a sequence; wherein the output of the detecting means is connectable to a set of delay means which uses the information received by said detecting means to generate a feedback signal to compensate timing errors in said register.
Where the register has a degree of hysteresis, this would produce a hunting effect whereby the skew varies around a mean. This hunting is typically +/xe2x88x9245 ps for registers using ALVCH technologyxe2x80x94it appears to be a result of the use of a non-differential external clock which is passed through an inverter internally to the register, as well as other factors. To remove this skew variation, the reference signal can be modulated in phase to produce a feedback signal which extends in time to be wider than the width of the hysteresis. The integrator will then have the effect within the feedback system of adjusting the clock phase to contain an equal number of 0s and 1s in a binary system, removing all hunting, without any detriment to the deskew accuracy.
In still another aspect of the invention, a self calibrating transmitter with expandable data width comprises at least one register having at least one channel having an input and output; a clock means for providing a clock signal to said register; a reference signal for supplying reference signals for deskewing said register""s channel output in relation to the reference signal; a phase comparator, one input of which is connected to the reference signal and another input is connected to a sense signal at the register""s output; and at least one feedback loop associated with the output of said phase comparator, the feedback loop comprising a set of delay means to compensate the timing errors in transmitter channels, wherein the reference signal is connectable to the input of the phase comparator; and an input of at least one said channel of said register is connectable to another signal for providing the sense signal to the phase comparator for deskewing the register.
It shall be mentioned that in this embodiment, the phase comparator serves as the detecting means for detecting a deviation from a predetermined level of probability of reading by said register a desired symbol on a boundary of two reference channel symbols in a sequence; wherein the information received by said phase comparator is used to generate a feedback signal to compensate timing errors in said register.
Furthermore, the present invention provides also the means for enhancing the timing accuracy for high speed digital data transmission systems experiencing asymmetry of rising and falling edges as illustrated in FIG. 8a, and/or inequity of duty cycles as shown in FIG. 8b. It shall be noted that rising edge in even data transmission slots and odd data transmission slots will be called even and odd rising edges, respectively, for the convenience of further explanation.
According to this aspect of the invention, the self-calibrating transmitter comprises the features as stated for the third embodiment, wherein said phase comparator comprises at least one channel for providing rising edge sense signal and at least one channel for providing falling edge sense signal for deskewing the register, while the calibration is effected for even rising, even falling and odd rising edges.
Thus, a system using the present invention will have a skew not more than the intra-register skew, which is caused for example by the parasitics of the device package and can be eliminated such as by compensatory track lengths in the printed circuit board (pcb) or by delays or verniers on each line or channel.
The above disclosed technique can be effectively applied for improving transmission parameters of high speed transmission systems including DDR systems, such as Rambus, or other systems in which the data rate is multiple of a main clock frequency.